46 lines
1.8 KiB
C
46 lines
1.8 KiB
C
#define W83627UHG_REG_SYSFANOUT_FREQUENCY 0x00
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#define W83627UHG_REG_SYSFANOUT_VALUE_SELECT 0x01
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#define W83627UHG_REG_CPUFANOUT_FREQUENCY 0x02
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#define W83627UHG_REG_CPUFANOUT_VALUE_SELECT 0x03
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#define W83627UHG_REG_FAN_CONF 0x04
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#define W83627UHG_REG_SYSTIN_TARGET_TEMP 0x05
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#define W83627UHG_REG_CPUTIN_TARGET_TEMP 0x06
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#define W83627UHG_REG_TARGET_TEMP_TOLERANCE 0x07
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#define W83627UHG_REG_SYSFANOUT_STOP_VALUE 0x08
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#define W83627UHG_REG_CPUFANOUT_STOP_VALUE 0x09
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#define W83627UHG_REG_SYSFANOUT_START_VALUE 0x0a
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#define W83627UHG_REG_CPUFANOUT_START_VALUE 0x0b
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#define W83627UHG_REG_SYSFANOUT_STOP_TIME 0x0c
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#define W83627UHG_REG_CPUFANOUT_STOP_TIME 0x0d
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#define W83627UHG_REG_FANOUT_STEPDOWN_TIME 0x0e
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#define W83627UHG_REG_FANOUT_STEPUP_TIME 0x0f
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#define W83627UHG_REG_FAN_CONF_2 0x12
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#define W83627UHG_REG_OVT_CONF 0x18
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#define W83627UHG_REG_CONFIG 0x40
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#define W83627UHG_REG_ISR_1 0x41
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#define W83627UHG_REG_ISR_2 0x42
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#define W83627UHG_REG_SMI_MASK_1 0x43
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#define W83627UHG_REG_SMI_MASK_2 0x44
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#define W83627UHG_REG_SMI_MASK_3 0x46
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#define W83627UHG_REG_FAN_DIVISOR 0x47
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#define W83627UHG_REG_SERIAL_BUS_ADDR 0x48
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#define W83627UHG_REG_CPUFANOUT_TEMP_SRC_SLCT 0x49
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#define W83627UHG_REG_SYSFANOUT_TEMP_SRC_SLCT 0x4a
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#define W83627UHG_REG_FAN_DIVISOR_2 0x4b
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#define W83627UHG_REG_SMI_OVT_CTRL 0x4c
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#define W83627UHG_REG_FAN_IN_OUT_CTRL 0x4d
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#define W83627UHG_REG_WINBOND_ID 0x4f
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#define W83627UHG_REG_BEEP_CTRL_1 0x56
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#define W83627UHG_REG_BEEP_CTRL_2 0x57
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#define W83627UHG_REG_CHIP_ID 0x58
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#define W83627UHG_REG_DIODE_SELECT_REG 0x59
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#define W83627UHG_REG_VBAT_MON_CTRL 0x5d
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#define W83627UHG_REG_CRIT_TEMP_EN 0x5e
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#define W83627UHG_REG_CPUFANOUT_MAX_OUT 0x67
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#define W83627UHG_REG_CPUFANOUT_OUT_STEP 0x68
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#define W83627UHG_REG_SYSFANOUT_CRIT_TEMP 0x6b
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#define W83627UHG_REG_CPUFANOUT_CRIT_TEMP 0x6c |