#define W83627UHG_REG_SYSFANOUT_FREQUENCY 0x00
#define W83627UHG_REG_SYSFANOUT_VALUE_SELECT 0x01
#define W83627UHG_REG_CPUFANOUT_FREQUENCY 0x02
#define W83627UHG_REG_CPUFANOUT_VALUE_SELECT 0x03
#define W83627UHG_REG_FAN_CONF 0x04
#define W83627UHG_REG_SYSTIN_TARGET_TEMP 0x05
#define W83627UHG_REG_CPUTIN_TARGET_TEMP 0x06
#define W83627UHG_REG_TARGET_TEMP_TOLERANCE 0x07
#define W83627UHG_REG_SYSFANOUT_STOP_VALUE 0x08
#define W83627UHG_REG_CPUFANOUT_STOP_VALUE 0x09
#define W83627UHG_REG_SYSFANOUT_START_VALUE 0x0a
#define W83627UHG_REG_CPUFANOUT_START_VALUE 0x0b
#define W83627UHG_REG_SYSFANOUT_STOP_TIME 0x0c
#define W83627UHG_REG_CPUFANOUT_STOP_TIME 0x0d
#define W83627UHG_REG_FANOUT_STEPDOWN_TIME 0x0e
#define W83627UHG_REG_FANOUT_STEPUP_TIME 0x0f
#define W83627UHG_REG_FAN_CONF_2 0x12
#define W83627UHG_REG_OVT_CONF 0x18

#define W83627UHG_REG_CONFIG 0x40
#define W83627UHG_REG_ISR_1 0x41
#define W83627UHG_REG_ISR_2 0x42
#define W83627UHG_REG_SMI_MASK_1 0x43
#define W83627UHG_REG_SMI_MASK_2 0x44
#define W83627UHG_REG_SMI_MASK_3 0x46
#define W83627UHG_REG_FAN_DIVISOR 0x47
#define W83627UHG_REG_SERIAL_BUS_ADDR 0x48
#define W83627UHG_REG_CPUFANOUT_TEMP_SRC_SLCT 0x49
#define W83627UHG_REG_SYSFANOUT_TEMP_SRC_SLCT 0x4a
#define W83627UHG_REG_FAN_DIVISOR_2 0x4b
#define W83627UHG_REG_SMI_OVT_CTRL 0x4c
#define W83627UHG_REG_FAN_IN_OUT_CTRL 0x4d
#define W83627UHG_REG_WINBOND_ID 0x4f

#define W83627UHG_REG_BEEP_CTRL_1 0x56
#define W83627UHG_REG_BEEP_CTRL_2 0x57
#define W83627UHG_REG_CHIP_ID 0x58
#define W83627UHG_REG_DIODE_SELECT_REG 0x59

#define W83627UHG_REG_VBAT_MON_CTRL 0x5d
#define W83627UHG_REG_CRIT_TEMP_EN 0x5e

#define W83627UHG_REG_CPUFANOUT_MAX_OUT 0x67
#define W83627UHG_REG_CPUFANOUT_OUT_STEP 0x68
#define W83627UHG_REG_SYSFANOUT_CRIT_TEMP 0x6b
#define W83627UHG_REG_CPUFANOUT_CRIT_TEMP 0x6c