172 lines
4.6 KiB
C
172 lines
4.6 KiB
C
#pragma once
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#include "common.h"
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// PCA9535 (DIPSW)
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#define PCA9535_IN0 0x00
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#define PCA9535_IN1 0x01
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#define PCA9535_OUT0 0x02
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#define PCA9535_OUT1 0x03
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#define PCA9535_INV0 0x04
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#define PCA9535_INV1 0x05
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#define PCA9535_CONF0 0x06
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#define PCA9535_CONF1 0x07
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/*
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W83627UHG:
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Configuration is based on HEFRAS
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Configuration 0:
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[Logical index port] 0x2e
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[Logical data port] 0x2f
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Configuration 1:
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[Logical index port] 0x4e
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[Logical data port] 0x4f
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Setup:
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! Select logical device 0 = FDC (in this case, we don't care)
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index = 0x07, data = 0x00
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index = 0x20, read data (Chip ID MSB)
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index = 0x21, read data (Chip ID LSB)
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[merge two bytes to get chip ID]
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! Select logical device B = HM
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* Read base address of address and data ports
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* Address = xxxh + 5h, Data = xxxh + 6h
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index = 0x07, data = 0x0b
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index = 0x60, read data (Base MSB)
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index = 0x61, read data (Base LSB)
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[merge two bytes to get address]
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ICH9 Smbus Controller:
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mxsmbus.sys -> io-controller-hub-9-datasheet.pdf, page 759
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PEC is disabled
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Requests are made using a virtual address.
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The physical address is *2 of the virtual, +1 for read.
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Commands:
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0: paddr = vaddr * 2 ; smb_cmd = quick
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1: paddr = vaddr * 2 + 1; smb_cmd = quick
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2: paddr = vaddr * 2 ; smb_cmd = byte
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3: paddr = vaddr * 2 + 1; smb_cmd = byte
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4: paddr = vaddr * 2 ; smb_cmd = byte data
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5: paddr = vaddr * 2 + 1; smb_cmd = byte data
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6: paddr = vaddr * 2 ; smb_cmd = word data
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7: paddr = vaddr * 2 + 1; smb_cmd = word data
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8: paddr = vaddr * 2 ; smb_cmd = block
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9: paddr = vaddr * 2 + 1; smb_cmd = block
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10: paddr = vaddr * 2 ; smb_cmd = process call
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11: paddr = vaddr * 2 ; smb_cmd = i2c read
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IOCTL_MXSMBUS_REQUEST:
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assert command <= 11
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0x25 bytes
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IOCTL_MXSMBUS_I2C:
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assert command <= 10
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0x27 bytes
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LPC device 0x00 = FPC
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LPC device 0x07 = W83627UHG
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smbus:
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0x801:
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PCA9535: 0000 100[Wr] | 8 bit addr/reg | [...
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amHmI2C: 0000 100[Wr] | 8 bit addr/reg | [...
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superio:
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0x803:
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amHmLPC:
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IOCTL_MXSUPERIO_READ:
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read 1: -> .. 0B 20 00
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<- .. .. .. XX
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read 2: -> .. 0B 21 00
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<- .. .. .. YY
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assert XXYY == 0xA020 (case 1) or 0xA230 (case 2)
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! SMBUS is I2C
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- ICH9: **host** (schematics, sheet 11)
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- EEPROM AT24C64AN: 0AE (schematics, sheet 10)
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- DDR2 DIMM A1: 0A0 (schematics, sheet 13)
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- DDR2 DIMM B1: 0A4 (schematics, sheet 14)
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- ICS9LPRS908: 0x?? (schematics, sheet 15)
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- W83627UHG LPC I/O: 0x?? (schematics, sheet 16) ((2E / 4E on a toggle?))
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- Mystery chips on the mezanine and keychip (schematics, sheet 17)
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- VRMs: 0x?? (schematics, sheet 27)
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! ??? is SPI
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! System SPI
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- SPI Flash ROM: ??? (schematics, sheet 11)
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-
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! LPC (superio) is its own thing?
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- ICH9: **host** (schematics, sheet 11)
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- TPM (schematics, sheet 10)
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- W83627UHC (schematics, sheet 16)
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*/
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// Keychip
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// #define DS_REG_ID 0xA0
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// #define DS_REG_ID_END 0xA7
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// #define DS_REG_STATUS 0xA8
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// #define DS_STATUS_FLAG_BUSY 2
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// #define DS_I2C_CHALLENGE_RESPONSE 0xB0
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#pragma pack(push, 1)
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typedef struct _MXSMBUS_REQUEST_PACKET {
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BYTE status;
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BYTE command;
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BYTE v_addr;
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BYTE command_code;
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BYTE nbytes;
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BYTE data[32];
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} MXSMBUS_REQUEST_PACKET, *PMXSMBUS_REQUEST_PACKET;
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typedef struct _MXSMBUS_I2C_PACKET {
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BYTE status;
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BYTE command;
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WORD v_addr;
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WORD command_code;
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BYTE nbytes;
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BYTE data[32];
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} MXSMBUS_I2C_PACKET, *PMXSMBUS_I2C_PACKET;
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#pragma pack(pop)
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typedef enum {
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ICH9_CMD_QUICK = 0b000,
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ICH9_CMD_BYTE = 0b001,
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ICH9_CMD_BYTE_DATA = 0b010,
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ICH9_CMD_WORD_DATA = 0b011,
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ICH9_CMD_PROCESS_CALL = 0b100,
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ICH9_CMD_BLOCK = 0b101,
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ICH9_CMD_I2C_READ = 0b110,
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ICH9_CMD_BLOCK_PROCESS = 0b111,
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} ich9_cmd_t;
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typedef enum {
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MXSMBUS_CMD_WRITE_QUICK = 0,
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MXSMBUS_CMD_READ_QUICK = 1,
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MXSMBUS_CMD_WRITE_BYTE = 2,
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MXSMBUS_CMD_READ_BYTE = 3,
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MXSMBUS_CMD_WRITE_BYTE_DATA = 4,
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MXSMBUS_CMD_READ_BYTE_DATA = 5,
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MXSMBUS_CMD_WRITE_WORD_DATA = 6,
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MXSMBUS_CMD_READ_WORD_DATA = 7,
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MXSMBUS_CMD_WRITE_BLOCK = 8,
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MXSMBUS_CMD_READ_BLOCK = 9,
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MXSMBUS_CMD_PROCESS_CALL = 10,
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MXSMBUS_CMD_I2C = 11,
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} mxsmbus_cmd_t;
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typedef BOOL smbus_callback_t(ich9_cmd_t cmd, WORD code, BYTE nbytes, BYTE* data);
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void smbus_install(BYTE v_addr, smbus_callback_t* write, smbus_callback_t* read);
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