2024-06-29 20:17:34 +00:00
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.syntax unified
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.arch armv8 - m.base
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.section .stack
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.align 3
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#ifndef Stack_Size
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.equ Stack_Size, 0x00000400
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#endif
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.global __StackTop
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.global __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifndef Heap_Size
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.equ Heap_Size, 0x00000100
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#endif
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.global __HeapBase
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.global __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .vectors
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.align 2
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.global __Vectors
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__Vectors:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts */
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.long BOD_IRQHandler
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.long WDT_IRQHandler
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.long EINT0_IRQHandler
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.long EINT1_IRQHandler
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.long GPAB_IRQHandler
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.long GPCDF_IRQHandler
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.long PWMA_IRQHandler
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.long Default_Handler
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.long TMR0_IRQHandler
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.long TMR1_IRQHandler
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.long TMR2_IRQHandler
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.long TMR3_IRQHandler
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.long UART0_IRQHandler
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.long UART1_IRQHandler
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.long SPI0_IRQHandler
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.long SPI1_IRQHandler
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.long SPI2_IRQHandler
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.long SPI3_IRQHandler
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.long I2C0_IRQHandler
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.long I2C1_IRQHandler
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.long CAN0_IRQHandler
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.long CAN1_IRQHandler
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.long SC012_IRQHandler
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.long USBD_IRQHandler
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.long PS2_IRQHandler
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.long ACMP_IRQHandler
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.long PDMA_IRQHandler
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.long I2S_IRQHandler
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.long PWRWU_IRQHandler
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.long ADC_IRQHandler
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.long Default_Handler
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.long RTC_IRQHandler
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.size __Vectors, . - __Vectors
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.text
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.thumb
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.thumb_func
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.align 2
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.global Reset_Handler
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.type Reset_Handler, % function
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Reset_Handler:
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2024-07-12 16:18:18 +00:00
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// Unlock Register
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ldr r0, =0x50000100 // REGCTL
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movs r1, #0x59
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str r1, [r0]
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movs r1, #0x16
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str r1, [r0]
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movs r1, #0x88
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str r1, [r0]
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// Init POR
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ldr r2, =0x50000024 // PORCTL
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movs r1, #0x5A
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lsls r1,r1,8
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adds r1,r1,#0xA5
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str r1, [r2]
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// Lock registers
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movs r1, #0
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str r1, [r0]
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2024-06-29 20:17:34 +00:00
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/* Single section scheme.
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*
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* The ranges of copy from/to are specified by following symbols
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* __etext: LMA of start of the section to copy from. Usually end of text
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* __data_start__: VMA of start of the section to copy to
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* __data_end__: VMA of end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, = __etext
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ldr r2, = __data_start__
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ldr r3, = __data_end__
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subs r3, r2
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2024-07-12 16:18:18 +00:00
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ble .L_loop1_done
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2024-06-29 20:17:34 +00:00
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.L_loop1:
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subs r3, #4
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2024-07-12 16:18:18 +00:00
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .L_loop1
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2024-06-29 20:17:34 +00:00
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.L_loop1_done:
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/* Single BSS section scheme.
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*
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* The BSS section is specified by following symbols
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* __bss_start__: start of the BSS section.
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* __bss_end__: end of the BSS section.
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*
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* Both addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, = __bss_start__
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ldr r2, = __bss_end__
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movs r0, 0
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subs r2, r1
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2024-07-12 16:18:18 +00:00
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ble .L_loop3_done
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2024-06-29 20:17:34 +00:00
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.L_loop3:
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subs r2, #4
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2024-07-12 16:18:18 +00:00
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str r0, [r1, r2]
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bgt .L_loop3
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2024-06-29 20:17:34 +00:00
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.L_loop3_done:
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#ifndef __ENTRY
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#define __ENTRY _entry
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#endif
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bl __ENTRY
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak Default_Handler
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.type Default_Handler, % function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, Default_Handler
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.endm
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler BOD_IRQHandler
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def_irq_handler WDT_IRQHandler
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def_irq_handler EINT0_IRQHandler
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def_irq_handler EINT1_IRQHandler
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def_irq_handler GPAB_IRQHandler
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def_irq_handler GPCDF_IRQHandler
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def_irq_handler PWMA_IRQHandler
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def_irq_handler TMR0_IRQHandler
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def_irq_handler TMR1_IRQHandler
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def_irq_handler TMR2_IRQHandler
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def_irq_handler TMR3_IRQHandler
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def_irq_handler UART0_IRQHandler
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def_irq_handler UART1_IRQHandler
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def_irq_handler SPI0_IRQHandler
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def_irq_handler SPI1_IRQHandler
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def_irq_handler SPI2_IRQHandler
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def_irq_handler SPI3_IRQHandler
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def_irq_handler I2C0_IRQHandler
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def_irq_handler I2C1_IRQHandler
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def_irq_handler CAN0_IRQHandler
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def_irq_handler CAN1_IRQHandler
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def_irq_handler SC012_IRQHandler
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def_irq_handler USBD_IRQHandler
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def_irq_handler PS2_IRQHandler
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def_irq_handler ACMP_IRQHandler
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def_irq_handler PDMA_IRQHandler
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def_irq_handler I2S_IRQHandler
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def_irq_handler PWRWU_IRQHandler
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def_irq_handler ADC_IRQHandler
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def_irq_handler RTC_IRQHandler
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/* ;int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0) */
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.align 2
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.thumb_func
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.type SH_DoCommand, % function
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SH_DoCommand:
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BKPT 0xAB /* ; Wait ICE or HardFault */
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2024-07-12 16:18:18 +00:00
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//ldr R3, = SH_Return
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2024-06-29 20:17:34 +00:00
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MOV R4, lr
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BLX R3 /* ; Call SH_Return. The return value is in R0 */
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BX R4 /* ; Return value = R0 */
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.size SH_DoCommand, . - SH_DoCommand
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.align 2
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.thumb_func
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.global __PC
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.type __PC, % function
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.end
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