// W83791D (H/W monitor)
// https://elixir.bootlin.com/linux/latest/source/drivers/hwmon/w83791d.c
// https://datasheetspdf.com/pdf-file/641504/Winbond/W83791D/1
// Bank 0
#define W83791D_REG_BANK 0x4E
#define W83791D_REG_TEMP2_CONFIG 0xC2
#define W83791D_REG_TEMP3_CONFIG 0xCA
#define W83791D_REG_TEMP1_0 0x27
#define W83791D_REG_TEMP1_1 0x39
#define W83791D_REG_TEMP1_2 0x3A
#define W83791D_REG_BEEP_CONFIG 0x4D
#define W83791D_REG_BEEP_CTRL_0 0x56
#define W83791D_REG_BEEP_CTRL_1 0x57
#define W83791D_REG_BEEP_CTRL_2 0xA3
#define W83791D_REG_GPIO 0x15
#define W83791D_REG_CONFIG 0x40
#define W83791D_REG_VID_FANDIV 0x47
#define W83791D_REG_DID_VID4 0x49
#define W83791D_REG_WCHIPID 0x58
#define W83791D_REG_CHIPMAN 0x4F  //
#define W83791D_REG_PIN 0x4B
#define W83791D_REG_I2C_SUBADDR 0x4A
#define W83791D_REG_ALARM1 0xA9
#define W83791D_REG_ALARM2 0xAA
#define W83791D_REG_ALARM3 0xAB
#define W83791D_REG_VBAT 0x5D
#define W83791D_REG_I2C_ADDR 0x48  // Used

#define W83791D_RAM_VCOREA 0x20
#define W83791D_RAM_VNIR0 0x21
#define W83791D_RAM_3V3 0x22
#define W83791D_RAM_VDD5 0x23
#define W83791D_RAM_12VIN 0x24
#define W83791D_RAM_N12VIN 0x25
#define W83791D_RAM_N5VIN 0x26
#define W83791D_RAM_TEMP 0x27
#define W83791D_RAM_FAN1 0x28
#define W83791D_RAM_FAN2 0x29
#define W83791D_RAM_FAN3 0x2a
#define W83791D_RAM_VCOREA_HIGH 0x2b
#define W83791D_RAM_VCOREA_LOW 0x2c
#define W83791D_RAM_VINR0_HIGH 0x2d
#define W83791D_RAM_VINR0_LOW 0x2e
#define W83791D_RAM_3V3_HIGH 0x2f
#define W83791D_RAM_3V3_LOW 0x30
#define W83791D_RAM_VDD5_HIGH 0x31
#define W83791D_RAM_VDD5_LOW 0x32
#define W83791D_RAM_12VIN_HIGH 0x33
#define W83791D_RAM_12VIN_LOW 0x34
#define W83791D_RAM_N12VIN_HIGH 0x35
#define W83791D_RAM_N12VIN_LOW 0x36
#define W83791D_RAM_N5VIN_HIGH 0x37
#define W83791D_RAM_N5VIN_LOW 0x38
#define W83791D_RAM_VTIN1_HIGH 0x39
#define W83791D_RAM_VTIN1_HYST 0x3a
#define W83791D_RAM_FAN1_LIMIT 0x3b
#define W83791D_RAM_FAN2_LIMIT 0x3c
#define W83791D_RAM_FAN3_LIMIT 0x3d

#define W83791D_VID_FAN_DIV 0x47
#define W83791D_VBAT_MONITOR_CONTROL 0x5d

// Beep flags
#define W83791D_BEEP0_EN_FAN2 0x80
#define W83791D_BEEP0_EN_FAN1 0x40
#define W83791D_BEEP0_EN_T2 0x20
#define W83791D_BEEP0_EN_T1 0x10
#define W83791D_BEEP0_EN_V5 0x08
#define W83791D_BEEP0_EN_V33 0x04
#define W83791D_BEEP0_EN_T3 0x02
#define W83791D_BEEP0_EN_V25A 0x01

#define W83791D_BEEP1_EN_G 0x80
#define W83791D_BEEP1_EN_VR1 0x40
#define W83791D_BEEP1_EN_VR0 0x20
#define W83791D_BEEP1_EN_CASO 0x10
#define W83791D_BEEP1_EN_FAN3 0x08
#define W83791D_BEEP1_EN_NV5 0x04
#define W83791D_BEEP1_EN_NV12 0x02
#define W83791D_BEEP1_EN_V13 0x01

#define W83791D_BEEP2_EN_USER 0x80
#define W83791D_BEEP2_EN_FAN5 0x40
#define W83791D_BEEP2_EN_FAN4 0x20
#define W83791D_BEEP2_EN_TART3 0x10
#define W83791D_BEEP2_EN_TART2 0x08
#define W83791D_BEEP2_EN_TART1 0x04
#define W83791D_BEEP2_EN_VBAT 0x02
#define W83791D_BEEP2_EN_VSB 0x01

// Config flags
#define W83791D_CONFIG_INIT 0x80
#define W83791D_CONFIG_IRQ_OUT 0x40
#define W83791D_CONFIG_IRQ_POL 0x40
#define W83791D_CONFIG_RESERVED 0x10
#define W83791D_CONFIG_INT_CLEAR 0x08
#define W83791D_CONFIG_IRQ_EN 0x04
#define W83791D_CONFIG_SMI_EN 0x02
#define W83791D_CONFIG_START 0x01

// VBAT monitor control
#define W83791D_VBMC_FANDIV3 0x80
#define W83791D_VBMC_FANDIV2 0x40
#define W83791D_VBMC_FANDIV1 0x20
#define W83791D_VBMC_EN_ALM_RSP 0x10
#define W83791D_VBMC_BJTS3 0x08
#define W83791D_VBMC_BJTS2 0x04
#define W83791D_VBMC_BJTS1 0x02
#define W83791D_VBMC_EN_VBAT_MINT 0x01

// Bank 1
#define W83791D_NONCRIT_TEMP_1 0x40
#define W83791D_CRIT_TEMP_1 0x41
#define W83791D_NONCRIT_TEMP_2 0x42
#define W83791D_CRIT_TEMP_2 0x43
#define W83791D_NONCRIT_TEMP_3 0x44
#define W83791D_CRIT_TEMP_3 0x45
#define W83791D_SENSOR_SBMUS_ADDRESS 0x4F

#define W83791D_VIN0 0x50  // VCORE
#define W83791D_VIN1 0x51  // VINR0
#define W83791D_VIN2 0x52  // +3.3 VIN
#define W83791D_VIN3 0x53  // +5 VIN
#define W83791D_VIN4 0x54  // +12 VIN
#define W83791D_VIN5 0x55  // -12 VIN
#define W83791D_VIN6 0x56  // -5 VIN
#define W83791D_VSB 0x57
#define W83791D_VBAT 0x58
#define W83791D_VINR1 0x59
#define W83791D_FAN1 0x5a
#define W83791D_FAN2 0x5b
#define W83791D_FAN3 0x5c
#define W83791D_TEMP1 0x5d
#define W83791D_TEMP2 0x5e
#define W83791D_TEMP3 0x5f
#define W83791D_CHASIS 0x50

#define W83791D_ENTITY_CPU 0x03
#define W83791D_ENTITY_SYSTEM 0x07
#define W83791D_ENTITY_MEMORY_MOD 0x08
#define W83791D_ENTITY_CHASIS 0x17
#define W83791D_ENTITY_FAN 0x1d
#define W83791D_ENTITY_MEMORY_DEV 0x20
